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Sunday 26 December 2010

CS302- Digital Logic Design Complete Finalterm Past Paper 2009

FINALTERM  EXAMINATION
Fall 2009
CS302- Digital Logic Design (Session - 4)
Ref No:
Time: 120 min
Marks: 75

Student Info
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Question No: 1    ( Marks: 1 )    - Please choose one
 NOR Gate can be used to perform the operation of AND, OR and NOT Gate

       FALSE
       TRUE
   
Question No: 2    ( Marks: 1 )    - Please choose one
 The output of an XNOR gate is 1 when ____________

I)    All the inputs are zero
II)   Any of the inputs is zero
III)  Any of the inputs is one
IV) All the inputs are one
       I Only
       IV Only
       I and IV only
       II and III only
  
Question No: 3    ( Marks: 1 )    - Please choose one
 NAND gate is formed by connecting _________

       ► AND Gate and then NOT Gate
       ► NOT Gate and then AND Gate
       ► AND Gate and then OR Gate
       ► OR Gate and then AND Gate
   
Question No: 4    ( Marks: 1 )    - Please choose one
 Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____

       ► Zero
       ► One
       ► Undefined
       ► No output as input is invalid
   
Question No: 5    ( Marks: 1 )    - Please choose one
 The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________


       Radiation-Erase programming method (REPM)
       In-System Programming (ISP)
       In-chip Programming (ICP)
       Electronically-Erase programming method(EEPM)
 
Question No: 6    ( Marks: 1 )    - Please choose one
 The ABEL symbol for “OR” operation is

       !
       &
       #
       $
   
Question No: 7    ( Marks: 1 )    - Please choose one
 If S=1 and R=1, then Q(t+1) = _________  for negative edge triggered flip-flop
       0
       1
       Invalid
       Input is invalid
   
Question No: 8    ( Marks: 1 )    - Please choose one
 The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
       Doesn’t have an invalid state
       Sets to clear when both J = 0 and K = 0
       It does not show transition on change in pulse
       It does not accept asynchronous inputs

Question No: 9    ( Marks: 1 )    - Please choose one
 For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________
       0
       1
       Q(t)
       Invalid
   
Question No: 10    ( Marks: 1 )    - Please choose one
 In asynchronous digital systems all the circuits change their state with respect to a common clock
       True
       False

Question No: 11    ( Marks: 1 )    - Please choose one
 A positive edge-triggered flip-flop changes its state when   ________________
       Low-to-high transition of clock
       High-to-low transition of clock
       Enable input (EN) is set
       Preset input (PRE) is set

Question No: 12    ( Marks: 1 )    - Please choose one
 ___________ is one of the examples of asynchronous inputs.
       J-K input
       S-R input
       D input
       Clear Input (CLR)
   
Question No: 13    ( Marks: 1 )    - Please choose one
 The _____________ input overrides the ________ input
       Asynchronous, synchronous
       Synchronous, asynchronous
       Preset input (PRE), Clear input (CLR)
       Clear input (CLR), Preset input (PRE)
 
Question No: 14    ( Marks: 1 )    - Please choose one
 Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.

       ► AND   
       ► NAND
       ► NOR
       ► XNOR
   
Question No: 15    ( Marks: 1 )    - Please choose one
 In ________ outputs depend only on the combination of current state and inputs.



       Mealy machine
       Moore Machine
       State Reduction table
       State Assignment table

Question No: 16    ( Marks: 1 )    - Please choose one
 ________ is used to simplify the circuit that determines the next state.
       State diagram
       Next state table
       State reduction
       State assignment
   
Question No: 17    ( Marks: 1 )    - Please choose one
 A multiplexer with a register circuit converts _________

       Serial data to parallel
       Parallel data to serial
       Serial data to serial
       Parallel data to parallel

Question No: 18    ( Marks: 1 )    - Please choose one
 In asynchronous transmission when the transmission line is idle, _________


       It is set to logic low
       It is set to logic high
       Remains in previous state
       State of transmission line is not used to start transmission
   
Question No: 19    ( Marks: 1 )    - Please choose one
 In the following statement
Z PIN 20 ISTYPE ‘reg.invert’;
The keyword “reg.invert” indicates ________


       An inverted register input
       An inverted register input at pin 20
       Active-high Registered Mode output
       Active-low Registered Mode output
   
Question No: 20    ( Marks: 1 )    - Please choose one
 A Nibble consists of _____ bits


       2

       4
       8
       16
  
Question No: 21    ( Marks: 1 )    - Please choose one
 The output of this circuit is always ________.


       1
       0
       A
      
   
Question No: 22    ( Marks: 1 )    - Please choose one
 At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?

       2
       4
       6
       8
   
Question No: 23    ( Marks: 1 )    - Please choose one
 A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.

       1110
       ► 0111
       ► 1000
       ► 1001
   
Question No: 24    ( Marks: 1 )    - Please choose one
 The high density FLASH memory cell is implemented using ______________


       1 floating-gate MOS transistor
       2 floating-gate MOS transistors
       4 floating-gate MOS transistors
       6 floating-gate MOS transistors

Question No: 25    ( Marks: 1 )    - Please choose one
 In order to synchronize two devices that consume and produce data at different rates, we can use _________


       Read Only Memory
       Fist In First Out Memory
       Flash Memory
       Fast Page Access Mode Memory
   
Question No: 26    ( Marks: 1 )    - Please choose one
 If the FIFO Memory output is already filled with data then ________


       It is locked; no data is allowed to enter
       It is not locked; the new data overwrites the previous data.
       Previous data is swapped out of memory and new data enters
       None of given options
   
Question No: 27    ( Marks: 1 )    - Please choose one
 The process of converting the analogue signal into a digital representation (code) is known as ___________



       Strobing
       Amplification
       Quantization
       Digitization
 
Question No: 28    ( Marks: 1 )    - Please choose one


Above is the circuit diagram of _______.

       Asynchronous up-counter
       Asynchronous down-counter
       Synchronous up-counter
       Synchronous down-counter
 
Question No: 29    ( Marks: 1 )    - Please choose one
   is an example of ______________

       Product of sum form

       Sum of product form
       Demorgans law
       Associative law
 
Question No: 30    ( Marks: 1 )    - Please choose one
 Q2 :=Q1 OR X OR Q3
The above ABEL expression will be

       Q2:= Q1 $ X $ Q3

       Q2:= Q1 # X # Q3

       Q2:= Q1 & X & Q3

       Q2:= Q1 ! X ! Q3


Question No: 31    ( Marks: 1 )
 How the “hour counter” is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)?
    
Question No: 32    ( Marks: 1 )
 The top of the stack contains the value “5” and bottom of the stack contains the value “6”, a pop (read data from stack) operation was executed, which value would be read?



   
Question No: 33    ( Marks: 2 )
 What kind of devices use the shift register based First In First Out (FIFO) memory?


Ans:

Question No: 34    ( Marks: 2 )
 Differentiate between positive-edge triggered flip-flop and negative edge-triggered flip-flop.


    
Question No: 35    ( Marks: 3 )
 Name some of the important operating characteristics of flip-flops 


Question No: 37    ( Marks: 3 )
 Write down at least three characteristics of serial in / serial out 4-bit right shift register.
    Ans:
Question No: 38    ( Marks: 5 )
 Explain Flash Analogue-to Digital Converter.

   
Question No: 39    ( Marks: 5 )
 Explain the next-state table with the help of a table for any sequential circuit.                           


Question No: 40    ( Marks: 10 )
 Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of “PRE” and “CLR” inputs on flip-flops.




    
Question No: 41    ( Marks: 10 )
 Explain the following in context of Memory:

Address signals
Data signals

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