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Sunday 26 December 2010

CS302- Digital Logic Design Complete Finalterm Paper 2009

FINALTERM  EXAMINATION
Fall 2009
CS302- Digital Logic Design (Session - 1)
Question No: 1    ( Marks: 1 )    - Please choose one
 The output of an AND gate is one when _______

       ► All of the inputs are one
       Any of the input is one
       Any of the input is zero
       All the inputs are zero
   
Question No: 2    ( Marks: 1 )    - Please choose one
 The OR Gate performs a Boolean _______ function


       Addition
       Subtraction
       ► Multiplication
       Division
 
Question No: 3    ( Marks: 1 )    - Please choose one
 A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.


       True
       False
   
Question No: 4    ( Marks: 1 )    - Please choose one
 The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?


       A > B = 1, A < B = 0, A < B = 1
       A > B = 0, A < B = 1, A = B = 0
       A > B = 1, A < B = 0, A = B = 0
       A > B = 0, A < B = 1, A = B = 1
   
Question No: 5    ( Marks: 1 )    - Please choose one


The diagram above shows the general implementation of _____ form
       ► boolean
       ► arbitrary
       ► POS
       ► SOP
   
Question No: 6    ( Marks: 1 )    - Please choose one
 The device shown here is most likely a

       Comparator
       Multiplexer
       Demultiplexer
       Parity generator
   
Question No: 7    ( Marks: 1 )    - Please choose one
 Demultiplexer converts _______ data to __________ data


       Parallel data, serial data
       Serial data, parallel data
       Encoded data, decoded data
       All of the given options.
   
Question No: 8    ( Marks: 1 )    - Please choose one
 Flip flops are also called _____________
       Bi-stable dualvibrators
       Bi-stable transformer
       Bi-stable multivibrators
       Bi-stable singlevibrators
 
Question No: 9    ( Marks: 1 )    - Please choose one
 If S=1 and R=0, then Q(t+1) = _________  for positive edge triggered flip-flop
       0
       1
       Invalid
       Input is invalid

Question No: 10    ( Marks: 1 )    - Please choose one
 If S=1 and R=1, then Q(t+1) = _________  for negative edge triggered flip-flop
       0
       1
       Invalid
       Input is invalid
   
Question No: 11    ( Marks: 1 )    - Please choose one
 The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
       Doesn’t have an invalid state
       Sets to clear when both J = 0 and K = 0
       It does not show transition on change in pulse
       It does not accept asynchronous inputs
  
Question No: 12    ( Marks: 1 )    - Please choose one
 The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

       Set-up time
           


       Hold time
       Pulse Interval time
       Pulse Stability time (PST)

   
Question No: 13    ( Marks: 1 )    - Please choose one
 We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________


       Using S-R Flop-Flop
       D-flipflop
       J-K flip-flop
       T-Flip-Flop
 
Question No: 14    ( Marks: 1 )    - Please choose one
 In asynchronous digital systems all the circuits change their state with respect to a common clock
       True
       False
   
Question No: 15    ( Marks: 1 )    - Please choose one
 A positive edge-triggered flip-flop changes its state when   ________________
       Low-to-high transition of clock
       High-to-low transition of clock
       Enable input (EN) is set
       Preset input (PRE) is set
   
Question No: 16    ( Marks: 1 )    - Please choose one
 A negative edge-triggered flip-flop changes its state when   ________________
       Enable input (EN) is set
       Preset input (PRE) is set
       Low-to-high transition of clock
        High-to-low transition of clock
 
Question No: 17    ( Marks: 1 )    - Please choose one
 A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is

       10 mW

       25 mW

       64 mW

       ► 1024
   
Question No: 18    ( Marks: 1 )    - Please choose one
 __________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay.
       Race condition
       Clock Skew
       Ripple Effect
       None of given options
   
Question No: 19    ( Marks: 1 )    - Please choose one
 A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
       3

       7

       8
       15

   
Question No: 20    ( Marks: 1 )    - Please choose one
 A divide-by-50 counter divides the input ______ signal to a 1 Hz signal.
       10 Hz
       50 Hz
       100 Hz
       500 Hz
   
Question No: 21    ( Marks: 1 )    - Please choose one
 The design and implementation of synchronous counters start from _________

       Truth table

       k-map
       state table
       state diagram
   
Question No: 22    ( Marks: 1 )    - Please choose one
 A synchronous decade counter will have _______ flip-flops
       3

       4
       7

       10

   
Question No: 23    ( Marks: 1 )    - Please choose one
 The output of this circuit is always ________.


       1
       0
       A
      
   
Question No: 24    ( Marks: 1 )    - Please choose one
 At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses?

       2
       4
       6
       8
Question No: 25    ( Marks: 1 )    - Please choose one
 In _______ the  output of the last flip-flop of the shift register is connected to the data input of the first flip-flop.
       Moore machine
       Meally machine
       Johnson counter
       Ring counter
   
Question No: 26    ( Marks: 1 )    - Please choose one
 In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register.

       Moore machine
       Meally machine
       Johnson counter
       Ring counter
   
Question No: 27    ( Marks: 1 )    - Please choose one
 Which is not characteristic of a shift register?
       Serial in/parallel in
       Serial in/parallel out
       Parallel in/serial out
       Parallel in/parallel out
   
Question No: 28    ( Marks: 1 )    - Please choose one
 Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)




       1100
       0011
       0000
       1111
   
Question No: 29    ( Marks: 1 )    - Please choose one
 The _________ of a ROM is the time it takes for the data to appear at the Data
Output of the ROM chip after an address is applied at the address input lines


       Write Time
       Recycle Time
       Refresh Time
       Access Time
   
Question No: 30    ( Marks: 1 )    - Please choose one
 The sequence of states that are implemented by a n-bit Johnson counter is

       n+2 (n plus 2)
       2n   (n multiplied by 2)
       2n   (2 raise to power n)
       n2   (n raise to power 2)
Question No: 31    ( Marks: 1 )
 In the statement  "X PIN 22 ISTYPE ‘reg.buffer"
What is the meaning of the keyword “reg.buffer”
Question No: 32    ( Marks: 1 )
 What are the two basic operations which are performed on memory?

   
Question No: 33    ( Marks: 2 )
 Explain state assignment process.
Question No: 34    ( Marks: 2 )
 What is RAM Stack, which register stores the address of the top of the stack?

   
Question No: 35    ( Marks: 3 )
 How can we calculate the frequency of an unknown signal?
    
Question No: 36    ( Marks: 3 )
 Explain dynamic RAM in your own words.
   
Question No: 37    ( Marks: 3 )
 Suppose a 2 bit up-down counter having states “A, B, C, D”. the counter counts upward when X=1 and downward when X=0. Write down IF-THEN-ELSE statements to show how present states change to next states and previous states.
   
Question No: 38    ( Marks: 5 )
 Explain memory read operation with the help of an example.

   
Question No: 39    ( Marks: 5 )
 Draw the next-state table of any sequential counter with the help of J-K flip flop transition
Question No: 40    ( Marks: 10 )
 You are given the diagram of up-down counter; explain how it works as an up and down counter.

    
Question No: 41    ( Marks: 10 )
 Consider a state sequence a, b, c, f, d, d, c, f, d, c, a, f, d, c. Starting from initial state a, draw a table for the inputs and outputs for the state diagram given below (up to first ten transitions).


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